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AI Chip Race Moves Beyond HBM to Advanced Packaging - Korea IT Times

Advanced packaging capacity is becoming a major constraint on AI chip supply, with TSMC’s CoWoS technology central to production. Chipmakers are funding capacity growth and pursuing alternative packaging methods, while Samsung draws on its memory, foundry, and packaging operations.

2026 IMPACT | SHINKO Reveals the Next Evolution of AI Advanced Packaging Substrates: From ABF and Glass Core to Hybrid RDL

SHINKO unveils a roadmap showing advanced packaging substrates evolving into integration platforms for AI/HPC, linking dies, HBM, power, and high-speed interconnects. Differentiation now hinges on materials, design, reliability, and advanced assembly to enable dense, multi-component packages.

AI Boom Makes Chip Packaging a New Battleground

AI demand is pushing advanced chip packaging into a battleground, led by Nvidia and TSMC, with panel-level packaging emerging as a key upgrade. Production capacity constraints drive investments across suppliers, with governments monitoring strategic implications and market forecasts predicting packaging surpassing traditional methods by 2026.

Samsung chief Lee visits Japan chip packaging lab - UM LEGACY PRESS LTD

Samsung Electronics Executive Chair Lee Jae-yong visited Japan to review the Advanced Package Lab in Yokohama and discuss progress on next-generation semiconductor packaging for AI chips, aiming to strengthen cooperation with local researchers and secure advanced packaging technologies.

NCKU 2026 Material Industry Forum: How Advanced Packaging, Testing, and Materials Innovation Are Redefining Taiwan’s Semiconductor Competitiveness

NCKU’s 11th Materials Industry Forum examined how advanced packaging, testing, and materials innovation are shaping Taiwan’s semiconductor competition. The article argues that AI hardware needs system-level integration beyond transistor scaling.

NVIDIA Developing NVHBM for Feynman GPUs – HardwareBrief.com

NVIDIA is pursuing NVHBM for its Feynman GPUs, with Samsung, Micron, and SK hynix sourcing the base die from TSMC at 3nm; Samsung may provide a production backup. The design uses a 1c sixth-generation DRAM core, promising higher bandwidth and lower power than HBM4E, while Samsung's foundry losses are expected to improve in 2026.

Mapping Exchange Phase In Quantum Dots With 3D Tomography

Sandia researchers adapted a phase-unwrapping method from digital holography to map exchange interactions in a silicon-germanium quantum dot device. The resulting 3D phase data may support more accurate device models and help tune qubit-control pulses.

Samsung Chief Visits Japan's Advanced Package Lab to Boost AI Chip Technology

Samsung Electronics Chairman Lee Jae-yong visits its Advanced Package Lab in Yokohama to advance AI chip packaging tech, signaling a multi-year, multi-hundred-million-dollar investment to boost competitiveness in AI-focused semiconductors.

Samsung would use TSMC's 3 nm for Nvidia's NVHBM memory - KultureGeek

Translated title. Original: Samsung utiliserait le 3 nm de TSMC pour la mémoire NVHBM de Nvidia - KultureGeek

Samsung reportedly agreed to have TSMC produce the base 3nm dies for Nvidia's NVHBM memory, enabling a common logic base across memory dies from multiple suppliers. The arrangement, if true, would standardize interfaces and tests but is not confirmed as an official contract.

Samsung chairman Lee visits Japan AI chip packaging R&D lab - Bytes Europe

Samsung Chairman Lee Jae-yong visited the Yokohama Advanced Package Lab, a new global R&D hub for AI chip packaging. The visit highlighted advances in materials and processes for semiconductor packaging and plans for a 350 billion won investment through 2028 to strengthen competitiveness, with emphasis on cooperation with Japanese suppliers.